1. Field of the Invention
The present invention relates to a semiconductor memory apparatus for precharging bit lines at a predetermined electric potential to read data therefrom.
2. Description of the Related Art
FIG. 1 is a circuit diagram of an example of the configuration of a static random access memory (SRAM). The drawing shows an example of a dual port SRAM having a single bit line to which precharging is performed. No writing circuit is shown in this drawing.
In FIG. 1, CELL(1,1) to CELL(m,n) represent SRAM cells arranged in a matrix of m lines and n rows, R.sub.-- B1 and R.sub.-- B2 to R.sub.--B.sub.n represent read bit lines, R.sub.-- W1 and R.sub.-- WB2 to R.sub.-- W.sub.m represent read word lines, W.sub.-- W1 and W.sub.-- W2 to W.sub.-- W.sub.m represent write word lines, NT.sub.PR1 and NT.sub.PR2 to NT.sub.PRn represent n-channel (N) metal oxide film semiconductor (NMOS) transistors for precharging the bit lines, NTSA.sub.PR1 represents a NMOS transistor for precharging an input node of a sense amplifier, NT.sub.SW1 and NT.sub.SW2 to NT.sub.SWn represent NMOS transistors serving as column switches, PU represents a precharge signal supply line, R.sub.-- C1 and R.sub.-- C2 to R.sub.-- Cn represent column switch supply lines, and SA represents a sense amplifier.
In FIG. 1, the SRAM cells CELL (1,1) to CELL (m,n) are TFT load type memory cells. Each, for example, the SRAM CELL (1,1), comprises a flip-flop including a pair of complementary (C) MOS inverters INV.sub.CL1 and INV.sub.CL2, inputs and outputs thereof being connected a cross-wise.
The memory nodes, which are outputs of the inverters INV.sub.CL1 in the SRAM cells CELL (1,1) to CELL (m,n), are connected to the read bit lines R.sub.-- B1, R.sub.-- B2 to R.sub.-- Bn through the word transistors R.sub.-- WT. The gates of the respective word transistors R.sub.-- WT are connected to the read word lines R.sub.-- W1 and R.sub.-- W2 to R.sub.-- Wm respectively.
The outputs of the respective inverters INV.sub.CL1, and the outputs of the inverters INV.sub.CL2 are connected to write bit lines, not shown, through the word transistors W.sub.-- WT1 and W WT2, respectively. The gates of the word transistors W.sub.-- WT1 and W.sub.-- WT2 are connected to the write word lines W.sub.-- W1 and W.sub.-- W2 to W.sub.-- Wm, respectively.
Specifically, the SRAM cells CELL(1,1) and CELL(2,1) to CELL(m,1) are connected to the bit line R.sub.-- B1 through the respective word transistors R.sub.-- WT, the SRAM cells CELL(1,2) and CELL(2,2) to CELL(m,2) are connected to the bit line R.sub.-- B2 through the respective word transistors R WT, and the SRAM cells CELL(1,n) and CELL(2,n) to CELL(m,n) are connected to the bit line R.sub.-- Bn through the respective word transistors R.sub.-- WT.
Also, the SRAM cells CELL(1,1) and CELL(1,2) to CELL(1,n) are connected to the read word line R.sub.-- W1 and the write word line W.sub.-- W2, the SRAM cells CELL(2,1) and CELL(2,2) to CELL(2,n) are connected the read word line R.sub.-- W2 and the write word line EW2, and the SRAM cells CELL(m,1) and CELL(m,2) to CELL(m,n) are connected to the read word line R.sub.-- Wm and the write word line W.sub.-- Wm.
The drains of the precharging NMOS transistors NT.sub.PR1 and NT.sub.PR2 to NT.sub.PRn are connected to the power supply lines of the power supply voltage vdd, and gates of the NMOS transistors NT.sub.PR1 and NT.sub.PR2 to NT.sub.prn are connected to the common precharge signal supply line PU.
The source of the NMOS transistor NT.sub.PR1 is connected to the bit line R.sub.-- B1, the source of the NMOS transistor NT.sub.PR2 is connected to the bit line R.sub.-- B2, and the source of the NMOS transistor NT.sub.PRn is connected to the bit line R.sub.-- Bn.
The NMOS transistor NT.sub.SW1 used as a column switch is provided between a connection point of the bit line R.sub.-- B1 and the source of the NMOS transistor NT.sub.PR1 and a connection point of the bit line R.sub.-- B1 and the sense amplifier SA. The gate of the NMOS transistor NT.sub.SW1 is connected to the column switch signal supply line R.sub.-- C1.
The NOS transistor NT.sub.SW2 used as a column switch is provided between a connection point of the bit line R.sub.-- B2 and the source of the NOMS transistor NT.sub.PR2 and a connection point of the bit line R.sub.-- B2 and the same amplifier SA. The gate of the NMOS transistor NT.sub.SW2 is connected to the column switch signal supply line R.sub.-- C2.
The NMOS transistor NT.sub.SWn used as a column switch is provided between a connection point of the bit line R.sub.-- Bn and the source of the NMOS transistor NT.sub.PRn, and a connection point of the bit line R.sub.-- Bn and the sense amplifier SA. The gate of the NMOS transistor NT.sub.SWn is connected to the column switch signal supply line R.sub.-- Cn.
The drain of the NMOS transistor NTSA.sub.PR1 for precharging the input node of the sense amplifier SA is connected to the supply line of the power supply voltage Vdd, the source of the NMOS transistor NTSA.sub.PR1 is connected to the node ND.sub.SA, which is a connection point between the bit lines R.sub.-- B1 and R.sub.-- B2 to R.sub.-- Bn and the sense amplifier SA, and the gate of the NMOS transistor NTSA.sub.PR1 is connected to the precharge signal supply line PU.
The sense amplifier SA is comprised of inverters IN.sub.SA1 INV.sub.SA2 and an NMOS transistor NT.sub.ST1.
The inverter INV.sub.SA1 and the inverter INV.sub.SA2 are connected in series, the input of the inverter INV.sub.SA1 is connected to the node ND.sub.SA, which is a connection point between the bit lines R.sub.-- B1 and R.sub.-- B2 to R.sub.-- Bn and the NMOS transistor NTSA.sub.PR1, and to the source of the NMOS transistor NT.sub.SA1. The output of the inverter INV.sub.SA2 functions as the output of the sense amplifier SA, and the output of the inverter INV.sub.SA2 is connected to the gate of the NMOS transistor ST.sub.SA1. The drain of the NMOS transistor NT.sub.SA1 is connected to the supply line of the power supply voltage Vdd.
Next, an explanation will be made of the data read operation of the circuit shown in FIG. 1 with reference to the timing chart in FIG. 2.
First, the read word lines R.sub.-- W1 to R.sub.-- Wn are set to the low level, and the precharge signal supply line PU is set to the high level.
As a result, the precharging NMOS transistors NT.sub.PR1 to NT.sub.PRn are turned on. The respective bit lines R.sub.-- B1 to R.sub.-- Bn are precharged at high level. Note that, an actual precharge level is defined as (Vdd-Vth-.DELTA.Vth). Here, Vth is the threshold voltage of the transistors, and .DELTA.Vth is the change of the threshold due to the substrate bias effect.
Also, since the precharge signal supply line PU is set to high level, the NMOS transistor NTSA.sub.PR1 is turned on, and the connection point between each of the read bit lines R.sub.-- B1 to R.sub.-- Bn and the sense amplifier SA, namely, the input node ND.sub.SA of the sense amplifier SA, is precharged at a high level.
Next, the level of the precharge signal supply line PU is changed from the high level to the low level, and the read word line R.sub.-- Wi selected by the address signal is set to the high level. As a result, the NMOS transistors NT.sub.PR1 to NT.sub.PRn and NTSA.sub.PR1 are turned OFF.
In response to the data stored in the SRAM cells CELL(i,l) to CELL(i,n) which are connected to the read word line R.sub.-- Wi set at a high level, the respective read bit lines R.sub.-- B1 to R.sub.-- Bn are discharged to a low level or are held at a high level.
One of n rows of the column switch signal supply bias R.sub.-- C1 to R.sub.-- Cn is set to the high level in accordance with the column address signal. As a result, one column switch NMOS transistor, whose gate is connected to the column switch signal supply line set to the high level, is turned ON, and the signal passing through the column switch NMOS transistor is input to the inverter INV.sub.SA1 in the sense amplifier SA.
In the above-mentioned apparatus, however, when the power supply voltage Vdd becomes low, the resultant precharge level is lowered, and, as a result, the sense amplifier SA may not amplify the input signal as in normal times.
When the sense amplifier SA is of a type of a sense amplifier in which a gate of an NMOS transistor receives the input signal, for example, a CMOS inverter, the high level input signal applied to the gate must be higher than the threshold voltage Vth of the transistor. That is, to ensure the normal operation of the sense amplifier SA, the following relationship must be satisfied:
(Vdd-Vth-.DELTA.Vth.gtoreq.Vth)
.thrfore.(Vdd.gtoreq.2Vth+.DELTA.Vth)
This, however, means that the sense amplifier SA cannot operate normally at the low power supply voltage.
As shown in FIG. 3, there has been proposed a circuit in which the precharging of the bit lines is carried out by p-channel MOS (PMOS) transistors PT.sub.PR1 to PT.sub.PRn and PTSA.sub.PR1, instead of the NMOS transistors. In the circuit, the column switches are comprised of transfer gates TFG.sub.SW1 to TFG.sub.SWn, which are comprised of NMOS transistors and PMOS transistors, with their source and their drains mutually connected, instead of the NMOS transistors. The respective gates of the NMOS transistors N.sub.1 to N.sub.n in the transfer gates TFG.sub.SW1 to TFG.sub.SWn are directly connected to the column switch signal supply lines R.sub.-- C1 to R.sub.-- Cn. The gates of the PMOS transistors P.sub.1 to P.sub.n in the transfer gates TFG.sub.SW1 to TFG.sub.SWn are connected to the column switch supply lines R.sub.-- C1 to R.sub.-- Cn through the inverters INV.sub.SW1 to INV.sub.SWn.
In this circuit, the power supply voltage by which the high level signal to the sense amplifier exceeds the threshold voltage Vth is Vdd.gtoreq.Vth. Thus, in this circuit, as compared with NMOS transistors, the sense amplifier can operate at a low level power supply voltage.
But in this case, since the bit line amplitude is increased from (Vdd-Vth-.DELTA.Vth) to Vdd, it suffers from the disadvantages of the increase of the operating current of the bit lines by charging and discharging.